Thin film transistor array panel and method manufacturing thereof

ABSTRACT

A thin film transistor array panel according to the present invention includes: an insulating substrate; a gate wire formed on the insulating substrate and including a plurality of gate portions and a gate connection connecting the gate portions; a data wire insulated from the gate wire and intersecting the date wire; a thin film transistor connected to the gate wire and the data wire; and a pixel electrode connected to the thin film transitor.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a thin film transistor array panel anda manufacturing method thereof.

(b) Description of the Related Art

A thin film transistor (TFT) array panel is widely unused in variousdisplay devices such as a notebook computer, a monitor, a televisionset, a mobile phone, etc. A thinner, lighter, cheaper, and strongflexible panel is required. The flexible panel may include a flexiblesubstrate on which TFTs are formed.

A flexible substrate includes a plastic substrate having highheat-resistance, high transmittance, and low contractibility, anextremely thin glass substrate which is hardly broken and easily bent,or a hybrid thereof.

However, a flexible substrate is apt to be curved by stress when itexperiences chemical vapor deposition (CVD) or sputtering of a siliconor metal thin film.

The stress exerted on a substrate, which is generated by deposition of agate wire, a data wire, or an amorphous silicon layer, etc., may bereleased when they are patterned by photo-etching. However, the stressin a direction along the length of the gate wire or the data wire is noteasily released. In addition, since only a small portion of an entirearea of a gate insulating layer and a passivation layer experienceetching, the stress maintains until the termination of a process tocause curve of the substrate.

The curvature of the substrate causes problems or impossibility inmisalignment in following photolithography processes and in incompleteevacuation in following coating processes. In addition, there is aproblem that the curved or crookedly display panel lowers the value ofthe products.

SUMMARY OF THE INVENTION

In order to overcome the above-described problems, the present inventionprovides a thin film transistor array panel and a manufacturing methodthereof divides a gate wire, a data wire, a passivation layer, and agate insulating layer into a plurality of patterns such that the stressexerted on the substrate is minimized.

In order to achieve the solution, a thin film transistor array panelaccording to the present invention includes: an insulating substrate; agate wire formed on the insulating substrate and including a pluralityof gate portions and a gate connection connecting the gate portions; adata wire insulated from the gate wire and intersecting the data wire; athin film transistor connected to the gate wire and the data wire; and apixel electrode connected to the thin film transistor. The data wireincludes a plurality of data portions and a data connection connectingthe data portions.

The thin film transistor array panel may further include a gateinsulating layer insulting the gate wire and the data wire and includinga plurality of portions and a passivation layer covering the thin filmtransistors and including a plurality of portions.

A thin film transistor array panel according to another embodiment ofthe present invention includes: an insulating substrate; a gate wireformed on the insulating substrate; a gate insulating layer formed onthe gate wire and including first and second contact holes; asemiconductor layer formed on a predetermined area of the gateinsulating layer; an ohmic contact layer formed on the semiconductorlayer and having a shape substantially the same as the semiconductorlayer except for a predetermined area of the semiconductor layer; a datawire insulated from the gate wire, intersecting the gate wire, andoverlapping the ohmic contact layer at least in part; a passivationlayer formed on the data wire and having a third contact hole exposingthe data wire; a pixel electrode formed on the passivation layer andconnected to the data wire through the third contact hole, wherein thegate wire includes first and second gate wire portions and a gateconnection formed on the same layer as the data wire, and the first andthe second gate wire portions are connected to the gate connectionthrough the first contact holes.

The data wire preferably includes first and second data wire portionsand a data connection formed on the same layer as the gate wire, and thefirst and the second data wire portions are connected to the dataconnection through the second contact holes.

The first and the second gate wire portion may include a gate lineextending in a direction and a gate electrode, which is a portion of thegate line, and the first gate wire portion further comprises a gate padprovided at an end of the gate line. The first and the second data wireportion may include a data line extending in a direction, a sourceelectrode, which is a portion of the data line and overlaps the ohmiccontact layer in part, and a drain electrode located opposite the sourceelectrode and overlapping the ohmic contact layer in part, and the firstdata wire portion further comprises a data pad provided at an end of thedata line.

The gate wire and the data wire intersect to define a pixel area, andportions of at least one of the gate insulating layer and thepassivation layer in the pixel electrode are removed. The gateinsulating layer and the passivation layer are preferably divided into aplurality of portions by an opening extending parallel to the gate wire,and the opening is preferably located between adjacent gate lines andconnected to the predetermined area of the pixel area.

A method of manufacturing a thin film transistor array panel includes:forming first and second gate wire and a data connection on aninsulating substrate; forming a gate insulating layer on the substrate;a semiconductor layer and an ohmic contact layer pattern on the gateinsulating layer partly overlapping the gate wire; forming first andsecond contact holes in the gate insulating layer; forming a gateconnection connected to the first and the second gate wires through thefirst contact holes and first and second data wires partly overlappingthe ohmic contact layer pattern connected to the data connection throughthe second contact holes on the substrate; forming an ohmic contactlayer by etching the ohmic contact layer pattern by using the data wireas a mask; forming a passivation layer having a third contact hole onthe substrate; and forming a pixel electrode connected to the data wirethrough the third contact hole on the passivation layer.

The formation of the first and the second contact holes includesformation of an opening for separating the gate insulating layer in thegate insulating layer.

The formation of the passivation layer includes formation of an openingfor separating the passivation layer in the passivation layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a layout view of a TFT array panel according to a firstembodiment of the present invention;

FIGS. 1B and 1C are sectional views of the TFT array panel shown in FIG.1A taken along the lines Ib-Ib′ and Ic-Ic′.

FIGS. 2A-5C are layout views sequentially illustrating a method ofmanufacturing a TFT array panel according to an embodiment of thepresent invention;

FIGS. 2B and 2C to FIGS. 5B to 5C are sectional views taken along thesection lines shown in FIGS. 2A to 5A;

FIGS. 6-9 are layout views of TFT array panels according to second tofifth embodiments of the present invention.

* Description of Reference Numerals in the Drawings * 110: insulatingsubstrate 120, 121, 123, 125: gate wire 140: gate insulating layer 141,142, 143: first to third contact holes 170, 171, 173, 175, 179: datawire 180: passivation layer 181, 182, 183: fourth to sixth contact holesO1, O2: opening

DETAILED DESCRITPION OF THE PREFERRED EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. The present invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein.

In the drawings, the thickness of layers, films and regions areexaggerated for clarity. Like numerals refer to like elementsthroughout. It will be understood that when an element such as a layer,film, region or substrate is referred to as being “on” another element,it can be directly on the other element or intervening elements may alsobe present. In contrast, when an element is referred to as being“directly on” another element, there are no intervening elementspresent.

Now, TFT array panels according to embodiments of the present inventionwill be described with reference to the accompanying drawings.

First to Fifth Embodiment

FIG. 1A is a layout view of a TFT array panel according to a firstembodiment of the present invention, and FIGS. 1B and 1C are sectionalviews of the TFT array panel shown in FIG. 1A taken along the linesIb-Ib′ and Ic-Ic′.

As shown in FIGS. 1A to 1C, portions 121 a, 121 b, 123 and 125 of a gatewire and a data connection 170 are formed on a transparent insulatingsubstrate 110.

The gate wire 120, 121, 123 and 125 includes a plurality of gate lines121, a plurality of gate electrodes 123, a plurality of gate pads 125,and a plurality of gate connections 120. The gate lines 121 extendsubstantially in a transverse direction and have a plurality ofsingularities. The gate electrodes 123 are connected to the gate lines121, and the gate pads 125 are provided at one ends of the gate lines121 and receive gate signals to transmit the gate lines 121.

Each gate line 121 includes a first gate line portion 121 a providedwith the gate pad 125 and a plurality of second gate line portions 121 bwithout the gate pads 125. The number of the first gate line portion 121a is one, while the number of the second gate line portions 121 b isseveral, and they are separated apart from each other by a predetermineddistance.

The gate connections 120 are formed on the same layer as data pads 179,which will be described layer, and connected to the disconnectedportions of the gate lines 121 through first contact holes 141 toelectrically connect them.

The data connections 170 extend perpendicular to the gate lines 121 andthey are separated from the gate lines 121 by a predetermined distance.

A gate insulating layer 140 is entirely formed on the substrateincluding the portions 121, 123 and 125 of the gate wire and the dataconnections 170. The gate insulating layer 140 has a plurality of firstcontact holes 141 exposing portions of the first gate line portions 121a and the second gate line portions 121 b, a plurality of second contactholes 142 exposing the data connections 170, and a plurality of thirdcontact holes 143 exposing the gate pads 125.

The contact holes are formed as shown in FIG. 1A, or, as shown in FIG.6, they are smaller than underlying metal wire (in a second embodiment).However, the metal wire has a dual-layered structure including Cr/Al andoveretching of Al due to different etching ratios for Al and Cr maycause undercut. Accordingly, it is preferable that the contact holes arelarger than the metal wire as in the first embodiment.

The gate insulating layer 140 has a plurality of sets of first andsecond openings O1 and O2 separating the gate insulating into upper andlower portions. In detail, the first openings O1 are formed by removingportions of the gate insulating layer 140 in pixel areas defined by thegate wire 120, 121, 123 and 125 and a data wire 170, 171, 173, 175 and179), which will be described later, and the second openings O2 arelocated between the adjacent gate lines 121 and extend parallel to thegate lines 121 to separate the gate insulating layer 140 into aplurality of separated upper and lower portions. The second openings O2are connected between the first openings O1.

The first openings O1 has various shapes of the removed areas dependingupon the stress exerted on the substrate 110 as shown in FIGS. 7 and 8(in third and fourth embodiments). Any shapes of the removed areas areallowable.

A semiconductor layer 154 preferably made of amorphous silicon is formedon the gate insulting layer 140 opposite the gate electrodes 123, and anohmic contact layer 163 and 165 preferably made of amorphous siliconheavily doped with impurity is formed thereon. The ohmic contact layer163 and 165 includes a plurality of pairs of a drain contact 165 and asource contact 163, and it has the same planar shape as thesemiconductor layer 154 except for predetermined portions of thesemiconductor layer 154. The predetermined portions include channelportions between source electrodes 173 and drain electrodes 175.

A plurality of portions 171, 173, 175 and 179 of a data wire and aplurality of gate connections 120 are formed on the ohmic contact layer163 and 165 and the gate insulating layer 140.

The data wire 170, 171, 173, 175 and 179 include a plurality of datalines 171, a plurality of source electrodes 173, a plurality of drainelectrodes 175, a plurality of data pads 179, and a plurality of dataconnections 170. The data lines 171 have a plurality of singularitiesand extend perpendicular to the gate lines 121 to define a plurality ofpixel areas. The source electrodes 173 are branched from the data lines171 and partly overlap the source contacts 163, and the drain electrodes175 are located opposite the source electrodes 173 with respect to thechannel areas and partly overlap the drain contacts 165. The data pads179 are connected to one ends of the data lines 171 and supplied datasignals from an external device.

In addition, each data line 171 includes a first data line portion 171 aprovided with the data pads 179 and a plurality of second data lineportions 171 b without the data pads 179. The number of the first dataline portion 171 a is one, while the number of the second data lineportions 171 b is several, and they are separated apart from each otherby a predetermined distance.

The data connections 170 are disposed on the same layer as the gate wire121, 123 and 125 and connected to the data lines 171 through secondcontact holes 142.

A passivation layer 180 is formed on the data wire 171, 173, 175 and 179and the gate connections 120. The passivation layer 180 is provided withforth to sixth contact holes 181-183. The fourth contact holes 181expose the drain electrodes 175, the fifth contact holes 182 expose thegate pads 125, and the sixth contact holes 183 expose the data pads 179.

A plurality of pixel electrodes 190, a plurality of subsidiary gate pads95, and a plurality of subsidiary data pads 97 are formed on thepassivation layer 180. The pixel electrodes 190 are connected to thedrain electrodes 175 through the fourth contact holes 181, thesubsidiary gate pads 95 are connected to the gate pads 125 through thefifth contact holes 182, and the subsidiary data pads 97 are connectedto the data pads 179 through the sixth contact holes 183.

The subsidiary gate pads 95 and the subsidiary data pads 97 are providedfor compensating the adhesiveness with external devices and forprotecting the pads 125 and 179 and their adoption is not indispensablebut optional.

Predetermined portions of the passivation layer 180 may be removed likethe gate insulating layer 140 (in a fifth embodiment). FIG. 9 is alayout view of a TFT array panel where predetermined portions of thegate insulating layer 140 and the passivation layer 180 are removed. Asshown in the figure, a plurality of openings O3 in the pixel areas and aplurality of openings O4 extending parallel to the gate lines 121 areprovided to further reduce the stress exerted on the substrate such thatthey separate the passivation layer 180 into upper and lower portions.

In this way, since predetermined intermediate portions of the gate wire120, 121, 123 and 125 and the data wire 170, 171, 173, 175 and 179 areremoved to separate the gate wire 120, 121, 123 and 125 and the datawire 170, 171, 173, 175 and 179 into a plurality of portions, the stressexerted along the length of the gate lines and the data lines arereduced.

In addition, although the gate insulating layer and the passivation inthe conventional art covers entire surface of the substrate to severelyexert the stress on the substrate, the present invention removesportions of those layers to reduce the stress, thereby decreasing thebend of the substrate.

A method of manufacturing the above-described TFT array panel isdescribed with reference to FIGS. 2A-5C.

FIGS. 2A-5C are layout views sequentially illustrating a method ofmanufacturing a TFT array panel according to an embodiment of thepresent invention, and FIGS. 2B and 2C to FIGS. 5B to 5C are sectionalviews taken along the section lines shown in FIGS. 2A to 5A.

First, as shown in FIGS. 2A-2C, a metal layer is formed on a transparentinsulating substrate 110 and patterned by photo-etching to form portionsof a gate wire 121, 123 and 125 and a plurality of data connections 170.

Referring to FIGS. 3A-3C, a gate insulating layer 140, an amorphoussilicon layer without doping, and a doped amorphous silicon layerheavily doped with impurity are formed on the gate wire 121, 123 and 125and the amorphous silicon layer and the doped amorphous silicon layerare photo-etched to form a semiconductor layer 154 and an ohmic contactlayer pattern 160A directly on the gate insulating layer 140 oppositethe gate electrodes 123.

Referring to FIGS. 4A-4C, the gate insulating layer 140 is patterned toform first to third contact holes 141, 142 and 143. Simultaneously,portions of the gate insulating layer 140 in pixel areas and portions ofthe gate insulating layer 140 extending parallel to the gate wire 121,123 and 125 are removed to form a plurality of first and second openingsO1 and O2.

Third contact holes 143 may be formed when contact holes are formed in apassivation layer. However, since both the passivation layer and thegate insulating layer 140 may be removed, the contact holes in thepassivation layer may be overetched to form undercut under the contactholes. Accordingly, it is preferable that the third contact holes 143are formed along with the first and the second contact holes 141 and142.

Referring to FIGS. 5A-5C, a metal layer is formed on the substrateprovided with the ohmic contact layer pattern 160A, and patterned byphoto-etching to form a data wire 171, 173, 175 and 179 and the gateconnections 120.

Next, portions of the ohmic contact layer pattern 160A disposed betweenthe source electrodes 173 and the drain electrodes 175 are removed usingthe data wire 171, 173, 175 and 179 as a mask to expose portions of thesemiconductor layer 154.

Finally, a passivation layer 180 is formed entirely on the substrateprovided with the data wire 171, 173, 175 and 179 and the gateconnections. The passivation layer 180 is patterned to form a pluralityof fourth to sixth contact holes 181-183. The fourth contact holes 181expose the drain electrodes 175, the fifth contact holes 182 expose thethird contact holes 143, and the sixth contact holes 183 expose the datapads 179.

In addition, a transparent metal layer is formed on the passivationlayer 180 and patterned to form a plurality of pixel electrodes 190, aplurality of subsidiary gate pads 95, and a plurality of subsidiary datapads 97. The pixel electrodes 190 are connected to the drain electrodes175 through the fourth contact holes 181, the subsidiary gate pads 95are connected to the gate pads 125 through the fifth contact holes 182,and the subsidiary data pads 97 are connected to the data pads 179through the sixth contact holes 183. (See FIGS. 1A-1C).

While the present invention has been described in detail with referenceto the preferred embodiments, those skilled in the art will appreciatethat various modifications and substitutions can be made thereto withoutdeparting from the spirit and scope of the present invention as setforth in the appended claims.

As described above, since portions of the gate wire and the data wireare removed to separate the wires into a plurality of portions, thestress exerted along the length of the wires are reduced.

In addition, the layers such as the gate insulating layer and thepassivation layer formed on entire area of the substrate are partlyremoved to further reduce the stress on the substrate. Accordingly, thebend of the substrate is minimized to secure high quality of the TFTarray panel.

1. A thin film transistor array panel comprising: an insulatingsubstrate; a gate wire formed on the insulating substrate and includinga plurality of gate portions and a gate connection connecting the gateportions; a data wire insulated from the gate wire and intersecting thedata wire; a thin film transistor connected to the gate wire and thedata wire; and a pixel electrode connected to the thin film transistor.2. The thin film transistor array panel of claim 1, wherein the datawire comprises a plurality of data portions and a data connectionconnecting the data portions.
 3. The thin film transistor array panel ofclaim 1, further comprising a gate insulating layer insulting the gatewire and the data wire and including a plurality of portions.
 4. Thethin film transistor array panel of claim 1, further comprising apassivation layer covering the thin film transistors and including aplurality of portions.
 5. The thin film transistor array panel of claim1, wherein the gate connection is disposed on the same layer as the dataportions, and connected to the gate portions through first contact holesprovided at the gate insulating layer.
 6. The thin film transistor arraypanel of claim 2, wherein the data connection is disposed on the samelayer as the gate portions, and connected to the data portions throughsecond contact holes provided at the gate insulating layer.
 7. A thinfilm transistor array panel comprising: an insulating substrate; a gatewire formed on the insulating substrate; a gate insulating layer formedon the gate wire and including first and second contact holes; asemiconductor layer formed on a predetermined area of the gateinsulating layer; an ohmic contact layer formed on the semiconductorlayer and having a shape substantially the same as the semiconductorlayer except for a predetermined area of the semiconductor layer; a datawire insulated from the gate wire, intersecting the gate wire, andoverlapping the ohmic contact layer at least in part; a passivationlayer formed on the data wire and having a third contact hole exposingthe data wire; a pixel electrode formed on the passivation layer andconnected to the data wire through the third contact hole, wherein thegate wire includes first and second gate wire portions and a gateconnection formed on the same layer as the data wire, and the first andthe second gate wire portions are connected to the gate connectionthrough the first contact holes.
 8. The thin film transistor array panelof claim 7, wherein the data wire includes first and second data wireportions and a data connection formed on the same layer as the gatewire, and the first and the second data wire portions are connected tothe data connection through the second contact holes.
 9. The thin filmtransistor array panel of claim 7, wherein the first and the second gatewire portion comprise a gate line extending in a direction and a gateelectrode, which is a portion of the gate line, and the first gate wireportion further comprises a gate pad provided at an end of the gateline.
 10. The thin film transistor array panel of claim 7, wherein thegate wire and the data wire intersect to define a pixel area, andportions of at least one of the gate insulating layer and thepassivation layer in the pixel electrode is removed.
 11. The thin filmtransistor array panel of claim 8, wherein the first and the second datawire portion comprise a data line extending in a direction, a sourceelectrode, which is a portion of the data line and overlaps the ohmiccontact layer in part, and a drain electrode located opposite the sourceelectrode and overlapping the ohmic contact layer in part, and the firstdata wire portion further comprises a data pad provided at an end of thedata line.
 12. The thin film transistor array panel of claim 10, whereinat least one of the gate insulating layer and the passivation layer isdivided into a plurality of portions by an opening extending parallel tothe gate wire, and the opening is located between adjacent gate linesand connected to the predetermined area of the pixel area.
 13. A methodof manufacturing a thin film transistor array panel, the methodcomprising: forming first and second gate wire and a data connection onan insulating substrate; forming a gate insulating layer on thesubstrate; a semiconductor layer and an ohmic contact layer pattern onthe gate insulating layer partly overlapping the gate wire; formingfirst and second contact holes in the gate insulating layer; forming agate connection connected to the first and the second gate wires throughthe first contact holes and first and second data wires partlyoverlapping the ohmic contact layer pattern connected to the dataconnection through the second contact holes on the substrate; forming anohmic contact layer by etching the ohmic contact layer pattern by usingthe data wire as a mask; forming a passivation layer having a thirdcontact hole on the substrate; and forming a pixel electrode connectedto the data wire through the third contact hole on the passivationlayer.
 14. The method of claim 14, wherein the formation of the firstand the second contact holes includes formation of an opening forseparating the gate insulating layer in the gate insulating layer. 15.The method of claim 13, wherein the formation of the passivation layerincludes formation of an opening for separating the passivation layer inthe passivation layer.